Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 490 of 765
Mar 7, 2023
Figure 12-88. Flowchart of Simplified I
2
C Address Field Transmission
Address field transmission
completed
Writing address and R/
W data to
SIOr (SDRmn[7:0])
Default setting
Generate
the start
condition.
Writing 1 to the SSmn bit
To secure a hold time of SCL signal
Responded ACK?
Yes
To data transmission flow
and data reception flow
Communication error
processing
Transfer end interrupt
generated?
No
ACK response from the slave will be confirmed
in PEFmn bit
.
If ACK (PEFmn = 0), to the next processing,
if NACK (
PEFmn = 1) to error processing.
No
Yes
Wait for address field transmission complete.
(Clear the interrupt request flag)
Transmitting address field
Enable serial output
Writing 1 to the SOEmn bit
Writing
0 to the CKOmn bit
Prepare to communicate the SCL signal is fall
Wait
Writing 0 to the SOmn bit
Set the SOmn bit to 0.
Transmitting address field
To serial operation enable status
For the initial setting, refer to Figure 12-86.

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English