RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 492 of 765
Mar 7, 2023
(1) Register setting
Figure 12-89. Example of Contents of Registers for Data Transmission of Simplified I
2
C (IIC00, IIC01)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSm
n
CCSm
n
STSm
n
SISmn
0
MDmn
2
MDmn
1
MDmn
0
0/1 0 0 0 0 0 0 0
Note 1
0 0
Note 1
1 0 0 1 0 0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this register, except
the TXEmn and RXEmn bits, during data transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEm
n
RXEm
n
DAPm
n
CKPm
n
EOCm
n
PTCm
n1
PTCm
n0
DIRmn
SLCm
n1
SLCm
n0
DLSm
n1
DLSm
n0
1 0 0 0 0 0 0 0 0 0 0
Note 2
1 0 1 1 1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) … During data transmission/reception, valid only lower 8-bits
(SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
Note 3
Transmit data setting
0
SIOr
(d) Serial output register m (SOm) … Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
CKOm
1
CKOm
0
SOm1
SOm0
0 0 0 0 0 0
/1
0/1
Note 4
0 0 0 0 0 0 0/1
/1
Note 4
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
SOEm
1
SOEm
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
(f) Serial channel start register m (SSm) … Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
SSm1
SSm0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1
(Note 1 to Note 4, and Remarks are listed on the next page.)
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