RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 538 of 765
Mar 7, 2023
Figure 13-19. Clock Stretching (2/2)
(2) When clock stretching occurs at the falling edge of the 9th clock for both master and slave
(master: transmission, slave: reception, and ACKE0 = 1)
Master
IICA
0
SCLA0
Slave
IICA0
SCLA0
ACKE0
Transfer line
SCLA0
SDAA
0
H
6 7 8 9 1 2 3
The clock is stretched after the 9
th
clock output for both the master
and slave.
Clock stretching from
the master and slave
Clock stretching from
the slave
IICA0 data write (release clock stretching)
FFH is written to IICA0 or
WREL0 is set to 1.
6 7 8 9 1 2 3
D2 D1 D
0
ACK
D7 D6 D5
Generated according to the previously set ACKE
0 value
Remark ACKE0: Bit 2 of IICA control register 00 (IICCTL00)
WREL0: Bit 5 of IICA control register 00 (IICCTL00)
Clock stretching is automatically generated depending on the setting of bit 3 (WTIM0) of IICA control register 00
(IICCTL00).
Normally, the reception side releases clock stretching when bit 5 (WREL0) of the IICCTL00 register is set to 1 or FFH is
written to IICA shift register 0 (IICA0), and the transmission side releases clock stretching when data is written to the
IICA0 register.
The master can also release clock stretching through either of the following methods.
●
By setting bit 1 (STT0) of the IICCTL00 register to 1
●
By setting bit 0 (SPT0) of the IICCTL00 register to 1
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