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Renesas RL78/G15 - Page 691

Renesas RL78/G15
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RL78/G15 CHAPTER 21 BCD CORRECTION CIRCUIT
R01UH0959EJ0110 Rev.1.10 Page 691 of 765
Mar 7, 2023
2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a
BCD code value
<1> The BCD code value from which subtraction is performed is stored in the A register.
<2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is in
binary, the calculation result in binary is stored in the A register, and the correction value is stored in the BCD
correction result register (BCDADJ).
<3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A
register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A register when it is
read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction
<2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled
state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and
AC flag) is restored by the RETI instruction.
An example is shown below.
Example: 91 52 = 39
Instruction A Register CY Flag AC Flag
BCDADJ
Register
MOV A, #91H ; <1>
91H
SUB A, #52H ; <2>
3FH 0 1 06H
SUB A, !BCDADJ ; <3>
39H 0 0

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