RL78/G15 CHAPTER 22 INSTRUCTION SET
R01UH0959EJ0110 Rev.1.10 Page 703 of 765
Mar 7, 2023
Table 22-5. Operation List (8/13)
Instruction
Group
Mnemonic Operand Bytes Clock Operation Flag
Note 1 Note 2
Z AC CY
8-bit
operation
CMP A, #byte 2 1 — A − byte × × ×
!addr16, #byte 4 1 4 (addr16) − byte × × ×
ES:!addr16, #byte 5 2 5 (ES:addr16) − byte × × ×
saddr, #byte 3 1 — (saddr) − byte × × ×
A, r
Note 3
2 1 — A − r × × ×
r, A 2 1 — r − A × × ×
A, !addr16 3 1 4 A − (addr16) × × ×
A, ES:!addr16 4 2 5 A − (ES:addr16) × × ×
A, saddr 2 1 — A − (saddr) × × ×
A, [HL] 1 1 4 A − (HL) × × ×
A, ES:[HL] 2 2 5 A − (ES:HL) × × ×
A, [HL+byte] 2 1 4 A − (HL + byte) × × ×
A, ES:[HL+byte] 3 2 5 A − ((ES:HL) + byte) × × ×
A, [HL+B] 2 1 4 A − (HL + B) × × ×
A, ES:[HL+B] 3 2 5 A − ((ES:HL) + B) × × ×
A, [HL+C] 2 1 4 A − (HL + C) × × ×
A, ES:[HL+C] 3 2 5 A − ((ES:HL) + C) × × ×
CMP0 A 1 1 — A − 00H × 0 0
X 1 1 — X − 00H × 0 0
B 1 1 — B − 00H × 0 0
C 1 1 — C − 00H × 0 0
!addr16 3 1 4 (addr16) − 00H × 0 0
ES:!addr16 4 2 5 (ES:addr16) − 00H × 0 0
saddr 2 1 — (saddr) − 00H × 0 0
CMPS X, [HL+byte] 3 1 4 X − (HL + byte) × × ×
X, ES:[HL+byte] 4 2 5 X − ((ES:HL) + byte) × × ×
16-bit
operation
ADDW AX, #word 3 1 — AX, CY ← AX + word × × ×
AX, AX 1 1 — AX, CY ← AX + AX × × ×
AX, BC 1 1 — AX, CY ← AX + BC × × ×
AX, DE 1 1 — AX, CY ← AX + DE × × ×
AX, HL 1 1 — AX, CY ← AX + HL × × ×
AX, !addr16 3 1 4 AX, CY ← AX + (addr16) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX + (ES:addr16) × × ×
AX, saddrp 2 1 — AX, CY ← AX + (saddrp) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX + (HL + byte) × × ×
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX + ((ES:HL) + byte) × × ×
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