Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 22 INSTRUCTION SET
R01UH0959EJ0110 Rev.1.10 Page 702 of 765
Mar 7, 2023
Table 22-5. Operation List (7/13)
Instruction
Group
Mnemonic Operand Bytes Clock Operation Flag
Note 1 Note 2
Z AC CY
8-bit
operation
AND A, [HL+C] 2 1 4 A ← A ∧ (HL + C) ×
A, ES:[HL+C] 3 2 5 A ← A ∧ ((ES:HL) + C) ×
OR A, #byte 2 1 — A ← A ∨ byte ×
saddr, #byte 3 2 — (saddr) ← (saddr) ∨ byte ×
A, r
Note 3
2 1 — A ← A ∨ r ×
r, A 2 1 — r ← r ∨ A ×
A, !addr16 3 1 4 A ← A ∨ (addr16) ×
A, ES:!addr16 4 2 5 A ← A ∨ (ES:addr16) ×
A, saddr 2 1 — A ← A ∨ (saddr) ×
A, [HL] 1 1 4 A ← A ∨ (HL) ×
A, ES:[HL] 2 2 5 A ← A ∨ (ES:HL) ×
A, [HL+byte] 2 1 4 A ← A ∨ (HL + byte) ×
A, ES:[HL+byte] 3 2 5 A ← A ∨ ((ES:HL) + byte) ×
A, [HL+B] 2 1 4 A ← A ∨ (HL + B) ×
A, ES:[HL+B] 3 2 5 A ← A ∨ ((ES:HL) + B) ×
A, [HL+C] 2 1 4 A ← A ∨ (HL + C) ×
A, ES:[HL+C] 3 2 5 A ← A ∨ ((ES:HL) + C) ×
XOR A, #byte 2 1 — A ← A ∀ byte ×
saddr, #byte 3 2 — (saddr) ← (saddr) ∀ byte ×
A, r
Note 3
2 1 — A ← A ∀ r ×
r, A 2 1 — r ← r ∀ A ×
A, !addr16 3 1 4 A ← A ∀ (addr16) ×
A, ES:!addr16 4 2 5 A ← A ∀ (ES:addr16) ×
A, saddr 2 1 — A ← A ∀ (saddr) ×
A, [HL] 1 1 4 A ← A ∀ (HL) ×
A, ES:[HL] 2 2 5 A ← A ∀ (ES:HL) ×
A, [HL+byte] 2 1 4 A ← A ∀ (HL + byte) ×
A, ES:[HL+byte] 3 2 5 A ← A ∀ ((ES:HL) + byte) ×
A, [HL+B] 2 1 4 A ← A ∀ (HL + B) ×
A, ES:[HL+B] 3 2 5 A ← A ∀ ((ES:HL) + B) ×
A, [HL+C] 2 1 4 A ← A ∀ (HL + C) ×
A, ES:[HL+C] 3 2 5 A ← A ∀ ((ES:HL) + C) ×

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English