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Renesas RL78/G15 User Manual

Renesas RL78/G15
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RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 88 of 765
Mar 7, 2023
Figure 3-24. Example of [HL + byte], [DE + byte]
Instruction code
OP-code
<2> byte
Target memory
FFFFFH
Memory
F0000H
Either pair of registers
<1> specifies the address where the
target array of data starts in the 64-Kbyte area from F0000H
to FFFFFH.
“byte” <2> specifies an offset within the array to the target
location in memory.
<1>
Address of an array
Target array
of data
rp (HL/DE)
<2> Offset
[HL + byte],
<1> <2>
[DE + byte]
<1> <2>
Other data in the array
Figure 3-25. Example of word[B], word[C]
Instruction code
OP
-code
Target memory
FFFFFH
Memory
F0000H
“word” <1> specifies the address where the target array of word-
sized data starts in the 64-Kbyte area from F0000
H to FFFFFH.
Either register <2> specifies an offset within the array to the
target location in memory.
<1
> Address of a word
within an array
Array of
word-sized
data
<2> Offset
word
<1>
[
B],
<2>
word
<1
>
[C],
<2>
Low Addr.
High Addr.
r (B
/C)
<2
>
Figure 3-26. Example of word[BC]
Instruction code
OP-code
Target memory
FFFFFH
Memory
F0000H
“word” <1> specifies the address where the target array of
word-sized data starts in the 64-Kbyte area from F0000H to
FFFFFH.
A pair of registers <2> specifies an offset within the array to
the target location in memory.
<1> Address of a word
within an array
Array of
word-sized
data
<2> Offset
word
<1>
[BC]
<2>
Low Addr.
High Addr.
rp (BC)
<2>
<1>

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Renesas RL78/G15 Specifications

General IconGeneral
BrandRenesas
ModelRL78/G15
CategoryMicrocontrollers
LanguageEnglish

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