Chapter 6: I/O Features in Cyclone IV Devices 6–35
True Differential Output Buffer Feature
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Differential SSTL I/O Standard Support in Cyclone IV Devices
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. Cyclone IV devices support differential
SSTL-2 and SSTL-18 I/O standards. The differential SSTL output standard is only
supported at
PLL#_CLKOUT
pins using two single-ended SSTL output buffers
(
PLL#_CLKOUTp
and
PLL#_CLKOUTn
), with the second output programmed to have
opposite polarity. The differential SSTL input standard is supported on the GCLK
pins only, treating differential inputs as two single-ended SSTL and only decoding
one of them.
The differential SSTL I/O standard requires two differential inputs with an external
reference voltage (
VREF
) as well as an external termination voltage (
VTT
) of 0.5 × V
CCIO
to which termination resistors are connected.
f For differential SSTL electrical specifications, refer to “Differential I/O Standard
Termination” on page 6–15 and the Cyclone IV Device Datasheet chapter.
1 Figure 6–8 on page 6–15 shows the differential SSTL Class I and Class II interface.
Differential HSTL I/O Standard Support in Cyclone IV Devices
The differential HSTL I/O standard is used for the applications designed to operate in
0V to 1.2V, 0V to 1.5V, or 0V to 1.8V HSTL logic switching range. Cyclone IV
devices support differential HSTL-18, HSTL-15, and HSTL-12 I/O standards. The
differential HSTL input standard is available on GCLK pins only, treating the
differential inputs as two single-ended HSTL and only decoding one of them. The
differential HSTL output standard is only supported at the
PLL#_CLKOUT
pins using
two single-ended HSTL output buffers (
PLL#_CLKOUT
p and
PLL#_CLKOUT
n), with the
second output programmed to have opposite polarity.
The differential HSTL I/O standard requires two differential inputs with an external
reference voltage (
VREF
), as well as an external termination voltage (
VTT
) of 0.5 × V
CCIO
to which termination resistors are connected.
f For differential HSTL signaling characteristics, refer to “Differential I/O Standard
Termination” on page 6–15 and the Cyclone IV Device Datasheet chapter.
1 Figure 6–7 on page 6–15 shows the differential HSTL Class I and Class II interface.
True Differential Output Buffer Feature
Cyclone IV devices true differential transmitters offer programmable
pre-emphasis—you can turn it on or off. The default setting is on.
Programmable Pre-Emphasis
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependant attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the V
OD
specification and the output impedance of the
transmitter. At high frequency, the slew rate may not be fast enough to reach full V
OD
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