Altera Cyclone IV - True Dual-Port Mode

Chapter 3: Memory Blocks in Cyclone IV Devices 3–11
Memory Modes
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 1
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations: two reads,
two writes, or one read and one write, at two different clock frequencies. Figure 3–10
shows Cyclone IV devices true dual-port memory configuration.
1 The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(18-bit with parity).
Tab le 3 –4 lists the possible M9K block mixed-port width configurations.
In true dual-port mode, M9K memory blocks support separate
wren and rden signals.
You can save power by keeping the
rden signal low (inactive) when not reading.
Read-during-write operations to the same address can either output “New Data” at
that location or “Old Data”. To choose the desired behavior, set the Read-During-
Write option to either New Data or Old Data in the RAM MegaWizard Plug-In
Manager in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write Operations” on page 3–15.
Figure 3–10. Cyclone IV Devices True Dual-Port Memory
(1)
Note to Figure 3–10:
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
clocken_a
rden_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
clocken_b
rden_b
aclr_b
q_b[]
Table 3–4. Cyclone IV Devices M9K Block Mixed-Width Configurations (True Dual-Port Mode)
Read Port
Write Port
8192
× 1 4096 × 2 2048 × 4 1024 × 8512× 16 1024 × 9 512 × 18
8192
× 1 vvvvv——
4096
× 2 vvvvv——
2048
× 4 vvvvv——
1024
× 8 vvvvv——
512
× 16 vvvvv——
1024
× 9—————vv
512
× 18—————vv