Altera Cyclone IV - Byte-Wide Multi-Device AP Configuration; Word-Wide Multi-Device AP Configuration

8–26 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Cyclone IV Device Handbook, May 2013 Altera Corporation
Volume 1
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0] pin from the flash and master device (set to the AP configuration scheme)
is connected to the slave devices set to the FPP configuration scheme, as shown in
Figure 8–8.
Word-Wide Multi-Device AP Configuration
The more efficient setup is one in which some of the slave devices are connected to the
LSB of the
DATA[7..0] and the remaining slave devices are connected to the MSB of
the
DATA[15..8] . In the word-wide multi-device AP configuration, the nCEO pin of the
master device enables two separate daisy chains of slave devices, allowing both
chains to be programmed concurrently, as shown in Figure 8–9.
Figure 8–8. Byte-Wide Multi-Device AP Configuration
Notes to Figure 8–8:
(1) Connect the pull-up resistors to the V
CCIO
supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the V
CCIO
supply voltage of the I/O bank in which the nCE pin resides.
(3) The
nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The
MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect
MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to Table 8–5 on
page 8–9. Connect the
MSEL pins directly to V
CCA
or GND.
(5) The AP configuration ignores the
WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the
WAIT signal from the Micron P30 or P33 flash.
(6) Connect the repeater buffers between the Cyclone IV E master device and slave devices for
DATA[15..0] and DCLK . All I/O inputs must maintain
a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration
and JTAG Pin I/O Requirements” on page 8–5.
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O
(5)
DATA[15..0]
PADD[23..0]
nCE
V
CCIO
(1)
V
CCIO
(1)
nCONFIG
nSTATUS
CONF_DONE
MSEL[3..0]
(4)
nCEO N.C. (3)
Cyclone IV E
Master DeviceMicron P30/P33 Flash
GND
DATA[7..0]
DCLK
nCE
nCONFIG
nSTATUS
CONF_DONE
MSEL[3..0]
(4)
nCEO
Cyclone IV E Slave Device
DATA[7..0]
DCLK
nCE
nCONFIG
nSTATUS
CONF_DONE
MSEL[3..0]
(4)
nCEO
Cyclone IV E Slave Device
V
CCIO
(2) V
CCIO
(2)
Buffers (6)
DQ[7..0]
DQ[7..0]
10 kΩ
10 kΩ
10 kΩ
10 kΩ
V
CCIO
(1)
10 kΩ