1–26 Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Cyclone IV Device Handbook, February 2015 Altera Corporation
Volume 2
Transceiver Clocking Architecture
The multipurpose PLLs and general-purpose PLLs located on the left side of the
device generate the clocks required for the transceiver operation. The following
sections describe the Cyclone IV GX transceiver clocking architecture:
■ “Input Reference Clocking” on page 1–27
■ “Transceiver Channel Datapath Clocking” on page 1–29
■ “FPGA Fabric-Transceiver Interface Clocking” on page 1–43
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