Altera Cyclone IV - Hard IP for PCI Express (Cyclone IV GX Devices Only)

Chapter 1: Cyclone IV FPGA Device Family Overview 1–11
Cyclone IV Device Family Architecture
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Figure 1–1 shows the structure of the Cyclone IV GX transceiver.
f For more information, refer to the Cyclone IV Transceivers Architecture chapter.
Hard IP for PCI Express (Cyclone IV GX Devices Only)
Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)
in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that
implements the PHY-MAC layer, Data Link Layer, and Transaction Layer
functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point
configurations. This pre-verified hard IP block reduces risk, design time, timing
closure, and verification. You can configure the block with the Quartus II software’s
PCI Express Compiler, which guides you through the process step by step.
f For more information, refer to the PCI Express Compiler User Guide.
Figure 1–1. Transceiver Channel for the Cyclone IV GX Device
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
Byte Serializer
8B10B Decoder
8B10B Encoder
Rate Match FIFO
Receiver Channel PCS Receiver Channel
PMA
Word Aligner
rx_datain
Deserializer
CDR
Transmitter Channel PCS
Transceiver Channel
PMA
tx_dataout
Serializer
PCI Express hard IP
FPGA
Fabric
PIPE Interface