Altera Cyclone IV - Simulation Requirements

2–22 Chapter 2: Cyclone IV Reset Control and Power Down
Simulation Requirements
Cyclone IV Device Handbook, September 2014 Altera Corporation
Volume 2
The deassertion of the busy signal indicates proper completion of the offset
cancellation process on the receiver channel.
Simulation Requirements
The following are simulation requirements:
■ The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port is not
instantiated, you must assert the
tx_digitalreset , rx_digitalreset , and
rx_analogreset signals appropriately for correct simulation behavior.
■ If the gxb_powerdown port is instantiated, and the other reset signals are not used,
you must assert the
gxb_powerdown signal for at least 1 s for correct simulation
behavior.
■ You can deassert the rx_digitalreset signal immediately after the rx_freqlocked
signal goes high to reduce the simulation run time. It is not necessary to wait for
t
LTD_Auto
(as suggested in the actual reset sequence).
■ The busy signal is deasserted after about 20 parallel reconfig_clk clock cycles in
order to reduce simulation run time. For silicon behavior in hardware, you can
follow the reset sequences described in the previous pages.
Figure 2–13. Sample Reset Sequence of a Receiver and Transmitter Channels-Receiver CDR in Automatic Lock Mode
with the Optional gxb_powerdown Signal
(1)
Notes to Figure 2–13:
(1) The gxb_powerdown signal must not be asserted during the offset cancellation sequence.
(2) For t
LTD_Auto
duration, refer to the Cyclone IV Device Datasheet chapter.
(3) The
busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the busy
signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
Output Status Signals
4
5
6
7
8
32
busy (3)
1
Reset/Power Down Signals
gxb_powerdown
pll_areset
tx_digitalreset
rx_analogreset
rx_digitalreset
pll_locked
rx_freqlocked
1 µs
t
LTD_Auto
(2)