3–14 Chapter 3: Memory Blocks in Cyclone IV Devices
Clocking Modes
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 1
Clocking Modes
Cyclone IV devices M9K memory blocks support the following clocking modes:
■ Independent
■ Input or output
■ Read or write
■ Single-clock
When using read or write clock mode, if you perform a simultaneous read or write to
the same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or I/O clock mode and choose
the appropriate read-during-write behavior in the MegaWizard Plug-In Manager.
1 Violating the setup or hold time on the memory block input registers might corrupt
the memory contents. This applies to both read and write operations.
1 Asynchronous clears are available on read address registers, output registers, and
output latches only.
Tab le 3 –5 lists the clocking mode versus memory mode support matrix.
Independent Clock Mode
Cyclone IV devices M9K memory blocks can implement independent clock mode for
true dual-port memories. In this mode, a separate clock is available for each port
(port A and port B).
clock A
controls all registers on the port A side, while
clock B
controls all registers on the port B side. Each port also supports independent clock
enables for port A and B registers.
Input or Output Clock Mode
Cyclone IV devices M9K memory blocks can implement input or output clock mode
for FIFO, single-port, true, and simple dual-port memories. In this mode, an input
clock controls all input registers to the memory block including data, address,
byteena
,
wren
, and
rden
registers. An output clock controls the data-output registers.
Each memory block port also supports independent clock enables for input and
output registers.
Table 3–5. Cyclone IV Devices Memory Clock Modes
Clocking Mode
True Dual-Port
Mode
Simple
Dual-Port
Mode
Single-Port
Mode
ROM Mode FIFO Mode
Independent v ——v —
Input or output vvvv—
Read or write — v ——v
Single-clock vvvvv
To Next Page
Loading...
