Altera Cyclone IV - Clock Frequency Compensation; XAUI Mode

Chapter 1: Cyclone IV Transceivers Architecture 1–67
Transceiver Functional Modes
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
Clock Frequency Compensation
In Serial RapidIO mode, the rate match FIFO compensates up to ±100 ppm (200 ppm
total) difference between the upstream transmitter and the local receiver reference
clock.
Rate matcher is an optional block available for selection in Serial RapidIO mode.
However, this block is not fully compliant to the SRIO specification. When enabled in
the ALTGX MegaWizard Plug-In Manager, the default settings are:
■ control pattern 1 = K28.5 with positive disparity
■ skip pattern 1 = K29.7 with positive disparity
■ control pattern 2 = K28.5 with negative disparity
■ skip pattern 2 = K29.7 with negative disparity
When enabled, the rate match FIFO operation begins after the link is synchronized
(indicated by assertion of
rx_syncstatus from the word aligner). When the rate
matcher receives either of the two 10-bit control patterns followed by the respective
10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the
rate match FIFO from overflowing or under-running. The rate match FIFO can
delete/insert a maximum of one skip pattern from a cluster.
1 The rate match FIFO may perform multiple insertion or deletion if the ppm difference
is more than the allowable 200 ppm range. Ensure that the ppm difference in your
system is less than 200 ppm.
XAUI Mode
XAUI mode provides the bonded (×4) transceiver channel datapath configuration for
XAUI protocol implementation. The Cyclone IV GX transceivers configured in XAUI
mode provides the following functions:
■ XGMII-to-PCS code conversion at transmitter datapath
■ PCS-to-XGMII code conversion at receiver datapath
■ channel deskewing of four lanes
■ 8B/10B encoding and decoding
■ IEEE P802.3ae-compliant synchronization state machine
■ clock rate compensation
The XAUI is a self-managed interface to transparently extend the physical reach of the
XGMII between the reconciliation sublayer and the PHY layer in the 10 Gbps LAN as
shown in Figure 1–62. The XAUI interface consists of four lanes, each running at
3.125 Gbps with 8B/10B encoded data for a total of actual 10 Gbps data throughput.
At the transmit side of the XAUI interface, the data and control characters are