Altera Cyclone IV - Reset Sequence in Loss of Link Conditions

Chapter 2: Cyclone IV Reset Control and Power Down 2–15
Transceiver Reset Sequences
September 2014 Altera Corporation Cyclone IV Device Handbook,
Volume 2
4. Wait for at least t
LTR_LTD_Manual
(the time between markers 6 and 7), then deassert
the
rx_locktorefclk signal. At the same time, assert the rx_locktodata signal
(marker 7). At this point, the receiver CDR enters lock-to-data mode and the
receiver CDR starts locking to the received data.
5. Deassert
rx_digitalreset at least t
LTD_Manual
(the time between markers 7 and 8)
after asserting the
rx_locktodata signal. At this point, the transmitter and receiver
are ready for data traffic.
Reset Sequence in Loss of Link Conditions
Loss of link can occur due to loss of local reference clock source or loss of the link due
to an unplugged cable. Other adverse conditions like loss of power could also cause
the loss of signal from the other device or link partner.
Loss of Local REFCLK or Other Reference Clock Condition
Should local reference clock input become disabled or unstable, take the following
steps:
1. Monitor
pll_locked signal. Pll_locked is de-asserted if local reference clock
source becomes unavailable.
2.
Pll_locked assertion indicates a stable reference clock because TX PLL locks to the
incoming clock. You can follow appropriate reset sequence provided in the device
handbook, starting from
pll_locked assertion.
Loss of Link Due To Unplugged Cable or Far End Shut-off Condition
Use one or more of the following methods to identify whether link partner is alive:
■ Signal detect is available in PCIe and Basic modes. You can monitor
rx_signaldetect signal as loss of link indicator. rx_signaldetect is asserted
when the link partner comes back up.
■ You can implement a ppm detector in device core for modes that do not have
signal detect to monitor the link. Ppm detector helps in identifying whether the
link is alive.
■ Data corruption or RX phase comp FIFO overflow or underflow condition in user
logic may indicate a loss of link condition.
Apply the following reset sequences when loss of link is detected:
■ For Automatic CDR lock mode:
a. Monitor
rx_freqlocked signal. Loss of link causes rx_freqlocked to be de-
asserted when CDR moves back to lock-to-data (LTD) mode.
b. Assert
rx_digitalreset .
c.
rx_freqlocked toggles over time when CDR switches between lock-to-
reference (LTR) and LTD modes.
d. If
rx_freqlocked goes low at any point, re-assert rx_digitalreset .
e. If data corruption or RX phase comp FIFO overflow or underflow condition is
observed in user logic, assert
rx_digitalreset for 2 parallel clock cycles, then
de-assert the signal.