Altera Cyclone IV - Reference Information

Chapter 2: Cyclone IV Reset Control and Power Down 2–23
Reference Information
September 2014 Altera Corporation Cyclone IV Device Handbook,
Volume 2
■ In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least
one parallel clock cycle before transmitting normal data for correct simulation
behavior.
Reference Information
For more information about some useful reference terms used in this chapter, refer to
the links listed in Table 2–7.
Table 2–7. Reference Information
Terms Used in this Chapter Useful Reference Points
Automatic Lock Mode page 2–8
Bonded channel configuration page 2–6
busy page 2–3
Dynamic Reconfiguration Reset Sequences page 2–19
gxb_powerdown page 2–3
LTD page 2–6
LTR page 2–6
Manual Lock Mode page 2–9
Non-Bonded channel configuration page 2–10
PCIe page 2–17
pll_locked page 2–3
pll_areset page 2–3
rx_analogreset page 2–2
rx_digitalreset page 2–2
rx_freqlocked page 2–3
tx_digitalreset page 2–2