Altera Cyclone IV - Basic Mode

1–48 Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Cyclone IV Device Handbook, February 2015 Altera Corporation
Volume 2
Basic Mode
The Cyclone IV GX transceiver channel datapath is highly flexible in Basic mode to
implement proprietary protocols. SATA, V-by-One, and Display Port protocol
implementations in Cyclone IV GX transceiver are supported with Basic mode.
Figure 1–44 shows the transceiver channel datapath supported in Basic mode.
Deterministic
Latency
Proprietary, CPRI,
OBSAI
TX PLL phase frequency detector (PFD) feedback,
registered mode FIFO, TX bit-slip control
“Deterministic Latency
Mode” on page 1–73
SDI SDI High-speed SERDES, CDR
“SDI Mode” on
page 1–76
Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 2 of 2)
Functional Mode Protocol Key Feature Reference
Figure 1–44. Transceiver Channel Datapath in Basic Mode
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS Transmitter Channel PMA
Serializer
PCIe Hard IP
FPGA
Fabric
PIPE Interface
Tx Phase
Comp
FIFO
tx_dataout
wr_clk rd_clk wr_clk rd_clk
Receiver Channel PCS Receiver Channel PMA
rx_datain
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Rx
Phase
Comp
FIFO