Altera Cyclone IV - Deskew FIFO

1–22 Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Cyclone IV Device Handbook, February 2015 Altera Corporation
Volume 2
synchronization state machine mode. In bit-slip mode, you can dynamically
enable the receiver bit reversal using the
rx_revbitorderwa port. When enabled,
the 8-bit or 10-bit data
D[7..0] or D[9..0] at the output of the word aligner is
rewired to
D[0..7] or D[0..9] respectively. Figure 1–20 shows the receiver bit
reversal feature.
1 When using the receiver bit reversal feature to receive MSB-to-LSB
transmission, reversal of the word alignment pattern is required.
■ Receiver bit-slip indicator—provides the number of bits slipped in the word
aligner for synchronization with
rx_bitslipboundaryselectout signal. For usage
details, refer to “Receive Bit-Slip Indication” on page 1–76.
Deskew FIFO
This module is only available when used for the XAUI protocol and is used to align all
four channels to meet the maximum skew requirement of 40 UI (12.8 ns) as seen at the
receiver of the four lanes. The deskew operation is compliant to the PCS deskew state
machine diagram specified in clause 48 of the IEEE P802.3ae specification.
The deskew circuitry consists of a 16-word deep deskew FIFO in each of the four
channels, and control logics in the central control unit of the transceiver block that
controls the deskew FIFO write and read operations in each channel.
For details about the deskew FIFO operations for channel deskewing, refer to “XAUI
Mode” on page 1–67.
Figure 1–20. Receiver Bit Reversal
(1)
Note to Figure 1–20:
(1) The rx_revbitordwa port is dynamic and is only available when the word aligner is configured in bit-slip mode.
Output of word aligner
before RX bit reversal
Output of word aligner
after RX bit reversal
rx_revbitordwa (1) = HIGH
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]