2–18 Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Cyclone IV Device Handbook, September 2014 Altera Corporation
Volume 2
PCIe Initialization/Compliance Phase
After the device is powered up, a PCIe-compliant device goes through the compliance
phase during initialization. The
rx_digitalreset
signal must be deasserted during
this compliance phase to achieve transitions on the
pipephydonestatus
signal, as
expected by the link layer. The
rx_digitalreset
signal is deasserted based on the
assertion of the
rx_freqlocked
signal.
During the initialization/compliance phase, do not use the
rx_freqlocked
signal to
trigger a deassertion of the
rx_digitalreset
signal. Instead, perform the following
reset sequence:
1. After power up, assert
pll_areset
for a minimum period of 1 s (the time
between markers 1 and 2). Keep the
tx_digitalreset
,
rx_analogreset
, and
rx_digitalreset
signals asserted during this time period. After you deassert the
pll_areset
signal, the multipurpose PLL starts locking to the input reference
clock.
2. After the multipurpose PLL locks, as indicated by the
pll_locked
signal going
high (marker 3), deassert
tx_digitalreset
. For a receiver operation, after
deassertion of busy signal, wait for two parallel clock cycles to deassert the
rx_analogreset
signal. After
rx_analogreset
is deasserted, the receiver CDR
starts locking to the receiver input reference clock.
3. Deassert both the
rx_analogreset
signal (marker 6) and
rx_digitalreset
signal
(marker 7) together, as indicated in Figure 2–10. After deasserting
rx_digitalreset
, the
pipephydonestatus
signal transitions from the transceiver
channel to indicate the status to the link layer. Depending on its status,
pipephydonestatus
helps with the continuation of the compliance phase. After
successful completion of this phase, the device enters into the normal operation
phase.
PCIe Normal Phase
For the normal PCIe phase:
1. After completion of the Initialization/Compliance phase, during the normal
operation phase at the Gen1 data rate, when the
rx_freqlocked
signal is
deasserted (marker 9 in Figure 2–10).
2. Wait for the
rx_freqlocked
signal to go high again. In this phase, the received data
is valid (not electrical idle) and the receiver CDR locks to the incoming data.
Proceed with the reset sequence after assertion of the
rx_freqlocked
signal.
3. After the
rx_freqlocked
signal goes high, wait for at least t
LTD_Manual
before
asserting
rx_digitalreset
(marker 12 in Figure 2–10) for two parallel receive
clock cycles so that the receiver phase compensation FIFO is initialized. For
bonded PCIe Gen 1 mode (×2 and ×4), wait for all the
rx_freqlocked
signals to go
high, then wait for t
LTD_Manual
before asserting
rx_digitalreset
for 2 parallel clock
cycles.
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