Altera Cyclone IV - External Memory Interface Specifications

1–32 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, December 2016 Altera Corporation
Volume 3
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
t
DUTY
— 45554555455545554555%
TCCS — — 200 — 200 — 200 — 200 — 200 ps
Output jitter
(peak to peak)
— — 500 — 500 — 550 — 600 — 700 ps
t
LOCK
(2)
——1—1—1—1— 1ms
Notes to Table 1–35:
(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.
Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) t
LOCK
is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices
(1), (3)
(Part 2 of 2)
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices
(1), (3)
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
f
HSCLK
(input
clock
frequency)
×10 10 437.5 10 370 10 320 10 320 10 250 MHz
×8 10 437.5 10 370 10 320 10 320 10 250 MHz
×7 10 437.5 10 370 10 320 10 320 10 250 MHz
×4 10 437.5 10 370 10 320 10 320 10 250 MHz
×2 10 437.5 10 370 10 320 10 320 10 250 MHz
×1 10 437.5 10 402.5 10 402.5 10 362 10 265 MHz
HSIODR
×10 100 875 100 740 100 640 100 640 100 500 Mbps
×8 80 875 80 740 80 640 80 640 80 500 Mbps
×7 70 875 70 740 70 640 70 640 70 500 Mbps
×4 40 875 40 740 40 640 40 640 40 500 Mbps
×2 20 875 20 740 20 640 20 640 20 500 Mbps
×1 10 437.5 10 402.5 10 402.5 10 362 10 265 Mbps
SW — — 400 — 400 — 400 — 550 — 640 ps
Input jitter
tolerance
— — 500 — 500 — 550 — 600 — 700 ps
t
LOCK
(2)
——1—1—1—1—1ms
Notes to Table 1–36:
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) t
LOCK
is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.