Programming Examples 5
Keysight Models 6811C, 6812C, and 6813C Programming Guide 265
Status byte register
This register summarizes the information from all other status groups as defined in
the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation. The
bit configuration is shown in Table 5-1.
The MSS bit
This is a real-time (unlatched) summary of all Status Byte register bits that are
enabled by the Service Request Enable register. MSS is set whenever the ac
source has one or more reasons for requesting service. *STB? reads the MSS in bit
position 6 of the response but does not clear any of the bits in the Status Byte
register.
The RQS bit
The RQS bit is a latched version of the MSS bit. Whenever the ac source requests
service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status
Byte register. When the controller does a serial poll, RQS is cleared inside the
register and returned in bit position 6 of the response. The remaining bits of the
Status Byte register are not disturbed.
The MAV bit and output queue
The Output Queue is a first-in, first-out (FIFO) data register that stores ac
source-to-controller messages until the controller reads them. Whenever the
queue holds one or more bytes, it sets the MAV bit (4) of the Status Byte register.
Command Action
*STB? reads the data in the register but does not clear it (returns MSS in bit 6).
Serial poll reads and clears the data in the register (returns RQS in bit 6)
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