NXP Semiconductors MC9S12G - Page 1234

Detailed Register Address Map
MC9S12G Family Reference Manual Rev.1.27
1236 NXP Semiconductors
0x0029 DBGXAH
R000000
Bit 17 Bit 16
W
0x002A DBGXAM
R
Bit 15 14 13 12 11 10 9 Bit 8
W
0x002B DBGXAL
R
Bit 7654321Bit 0
W
0x002C DBGADH
R
Bit 15 14 13 12 11 10 9 Bit 8
W
0x002D DBGADL
R
Bit 7654321Bit 0
W
0x002E DBGADHM
R
Bit 15 14 13 12 11 10 9 Bit 8
W
0x002F DBGADLM
R
Bit 7654321Bit 0
W
0x0030–0x033 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0030-
0x0033
Reserved
R00000000
W
0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0034
CPMU
SYNR
R
VCOFRQ[1:0] SYNDIV[5:0]
W
0x0035
CPMU
REFDIV
R
REFFRQ[1:0]
00
REFDIV[3:0]
W
0x0036
CPMU
POSTDIV
R000
POSTDIV[4:0]
W
0x0037 CPMUFLG
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF OSCIF
UPOSC
W
0x0038 CPMUINT
R
RTIE
00
LOCKIE
00
OSCIE
0
W
0x0039 CPMUCLKS
R
PLLSEL PSTP
00
PRE PCE
RTI
OSCSEL
COP
OSCSEL
W
0x003A CPMUPLL
R0 0
FM1 FM0
0000
W
0x003B CPMURTI
R
RTDECRTR6RTR5RTR4RTR3RTR2RTR1RTR0
W
0x003C CPMUCOP
R
WCOP RSBCK
000
CR2 CR1 CR0
WWRTMAS
K
0x0020–0x002F Debug Module (DBG)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0