NXP Semiconductors MC9S12G - Page 191

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 193
0x0249
PTIS
R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
0x024A
DDRS
R
DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
0x024B
Reserved
R00000000
W
0x024C
PERS
R
PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
0x024D
PPSS
R
PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
0x024E
WOMS
R
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
0x024F
PRR0
R
PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0
W
0x0250
PTM
R000000
PTM1 PTM0
W
0x0251
PTIM
R000000PTIM1PTIM0
W
0x0252
DDRM
R000000
DDRM1 DDRM0
W
0x0253
Reserved
R00000000
W
0x0254
PERM
R000000
PERM1 PERM0
W
0x0255
PPSM
R000000
PPSM1 PPSM0
W
0x0256
WOMM
R000000
WOMM1 WOMM0
W
0x0257
PKGCR
R
APICLKS7
0000
PKGCR2 PKGCR1 PKGCR0
W
Table 2-21. Block Register Map (G3) (continued)
Global Address
Register Name
Bit 7654321Bit 0
= Unimplemented or Reserved