NXP Semiconductors MC9S12G - Page 192

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
194 NXP Semiconductors
0x0258
PTP
R0 0
PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
0x0259
PTIP
R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
0x025A
DDRP
R0 0
DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
0x025B
Reserved
R00000000
W
0x025C
PERP
R0 0
PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
0x025D
PPSP
R0 0
PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
0x025E
PIEP
R0 0
PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
0x025F
PIFP
R0 0
PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
0x0260–0x0261
Reserved
R
Reserved for ACMP
W
0x0262–0x0267
Reserved
R00000000
W
0x0268
PTJ
R0000
PTJ3 PTJ2 PTJ1 PTJ0
W
0x0269
PTIJ
R 0 0 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0
W
0x026A
DDRJ
R0000
DDRJ3 DDRJ2 DDRJ1 DDRJ0
W
0x026B
Reserved
R00000000
W
0x026C
PERJ
R0000
PERJ3 PERJ2 PERJ1 PERJ0
W
Table 2-21. Block Register Map (G3) (continued)
Global Address
Register Name
Bit 7654321Bit 0
= Unimplemented or Reserved