Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 195
0x026D
PPSJ
R0000
PPSJ3 PPSJ2 PPSJ1 PPSJ0
W
0x026E
PIEJ
R0000
PIEJ3 PIEJ2 PIEJ1 PIEJ0
W
0x026F
PIFJ
R0000
PIFJ3 PIFJ2 PIFJ1 PIFJ0
W
0x0270
PT0AD
R0000
PT0AD3 PT0AD2 PT0AD1 PT0AD0
W
0x0271
PT1AD
R
PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
W
0x0272
PTI0AD
R 0 0 0 0 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0
W
0x0273
PTI1AD
R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0
W
0x0274
DDR0AD
R0000
DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0
W
0x0275
DDR1AD
R
DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0
W
0x0276
Reserved
R00000000
W
0x0277
Reserved
R00000000
W
0x0278
PER0AD
R0000
PER0AD3 PER0AD2 PER0AD1 PER0AD0
W
0x0279
PER1AD
R
PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
W
0x027A
PPS0AD
R0000
PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0
W
0x027B
PPS1AD
R
PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0
W
Table 2-21. Block Register Map (G3) (continued)
Global Address
Register Name
Bit 7654321Bit 0
= Unimplemented or Reserved