NXP Semiconductors MC9S12G - Page 195

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 197
2.4.3.1 Port A Data Register (PORTA)
2.4.3.2 Port B Data Register (PORTB)
Address 0x0000 (G1) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
W
Reset00000000
Address 0x0000 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-2. Port A Data Register (PORTA)
Table 2-22. PORTA Register Field Descriptions
Field Description
7-0
PA
Port A general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Address 0x0001 (G1) Access: User read/write
1
76543210
R
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
W
Reset00000000
Address 0x0001 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-3. Port B Data Register (PORTB)