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NXP Semiconductors MC9S12G - Page 201

NXP Semiconductors MC9S12G
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Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 203
2.4.3.11 Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR)
Table 2-31. DDRE Register Field Descriptions
Field Description
1-0
DDRE
Port E Data Direction
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x000C (G1) Access: User read/write
1
1
Read:Anytime in normal mode.
Write:Anytime, except BKPUE, which is writable in special mode only.
76543210
R0
BKPUE
0
PDPEE PUPDE PUPCE PUPBE PUPAE
W
Reset01010000
Address 0x000C (G2, G3) Access: User read/write
76543210
R0
BKPUE
0
PDPEE
0000
W
Reset01010000
Figure 2-12. Ports A, B, C, D, E, BKGD pin Pullup Control Register (PUCR)
Table 2-32. PUCR Register Field Descriptions
Field Description
6
BKPUE
BKGD pin Pullup Enable—Enable pullup device on pin
This bit configures whether a pullup device is activated, if the pin is used as input. If a pin is used as output this bit
has no effect. Out of reset the pullup device is enabled.
1 Pullup device enabled
0 Pullup device disabled
4
PDPEE
Port E Pulldown Enable—Enable pulldown devices on all port input pins
This bit configures whether a pulldown device is activated on all associated port input pins. If a pin is used as output
or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled.
1 Pulldown devices enabled
0 Pulldown devices disabled
3
PUPDE
Port D Pullup Enable—Enable pullup devices on all port input pins
This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pullup devices enabled
0 Pullup devices disabled

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