Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
202 NXP Semiconductors
2.4.3.9 Port E Data Register (PORTE)
2.4.3.10 Port E Data Direction Register (DDRE)
Table 2-29. DDRD Register Field Descriptions
Field Description
7-0
DDRD
Port D Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0008 Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R000000
PE1 PE0
W
Reset00000000
Figure 2-10. Port E Data Register (PORTE)
Table 2-30. PORTE Register Field Descriptions
Field Description
1-0
PE
Port E general-purpose input/output data—Data Register
When not used with an alternative signal, this pin can be used as general-purpose I/O.
In general-purpose output mode the port data register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Address 0x0009 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R000000
DDRE1 DDRE0
W
Reset00000000
Figure 2-11. Port E Data Direction Register (DDRE)
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