NXP Semiconductors MC9S12G - Page 199

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 201
2.4.3.7 Port C Data Direction Register (DDRC)
2.4.3.8 Port D Data Direction Register (DDRD)
Address 0x0006 (G1) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRC7 DDRC6 DDRC5 DDRA4 DDRC3 DDRC2 DDRC1 DDRC0
W
Reset00000000
Address 0x0006 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-8. Port C Data Direction Register (DDRC)
Table 2-28. DDRC Register Field Descriptions
Field Description
7-0
DDRC
Port C Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0007 (G1) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
W
Reset00000000
Address 0x0007 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-9. Port D Data Direction Register (DDRD)