NXP Semiconductors MC9S12G - Page 198

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
200 NXP Semiconductors
2.4.3.6 Port D Data Register (PORTD)
Table 2-26. PORTC Register Field Descriptions
Field Description
7-0
PC
Port C general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Address 0x0005 (G1) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
W
Reset00000000
Address 0x0005 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-7. Port D Data Register (PORTD)
Table 2-27. PORTD Register Field Descriptions
Field Description
7-0
PD
Port D general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.