NXP Semiconductors MC9S12G - Page 197

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 199
2.4.3.4 Port B Data Direction Register (DDRB)
2.4.3.5 Port C Data Register (PORTC)
Address 0x0003 (G1) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
W
Reset00000000
Address 0x0003 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-5. Port B Data Direction Register (DDRB)
Table 2-25. DDRB Register Field Descriptions
Field Description
7-0
DDRB
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0004 (G1) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
W
Reset00000000
Address 0x0004 (G2, G3) Access: User read only
76543210
R00000000
W
Reset00000000
Figure 2-6. Port C Data Register (PORTC)