NXP Semiconductors MC9S12G - Page 203

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 205
2.4.3.12 ECLK Control Register (ECLKCTL)
2.4.3.13 IRQ Control Register (IRQCR)
Address 0x001C Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
Reset:11000000
Figure 2-13. ECLK Control Register (ECLKCTL)
Table 2-33. ECLKCTL Register Field Descriptions
Field Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
NCLKX2
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
5
DIV16
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
EDIV
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
Address 0x001E Access: User read/write
1
76543210
R
IRQE IRQEN
000000
W
Reset00000000
Figure 2-14. IRQ Control Register (IRQCR)