NXP Semiconductors MC9S12G - Page 206

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
208 NXP Semiconductors
2.4.3.17 Port T Data Direction Register (DDRT)
Table 2-36. PTIT Register Field Descriptions
Field Description
7-0
PTIT
Port T input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0242 (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset00000000
Address 0x0242 (G3) Access: User read/write
1
76543210
R 0 0
DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset00000000
Figure 2-18. Port T Data Direction Register (DDRT)
Table 2-37. DDRT Register Field Descriptions
Field Description
7-0
DDRT
Port T data direction—
This bit determines whether the pin is a general-purpose input or output.
1 Associated pin configured as output
0 Associated pin configured as input