NXP Semiconductors MC9S12G - Page 207

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 209
2.4.3.18 Port T Pull Device Enable Register (PERT)
Address 0x0244 (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
Reset00000000
Address 0x0244 (G3) Access: User read/write
1
76543210
R0 0
PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
Reset00000000
Figure 2-19. Port T Pull Device Enable Register (PERT)
Table 2-38. PERT Register Field Descriptions
Field Description
7-2
PERT
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
1
PERT
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If this pin is used as IRQ only a pullup device can be enabled.
1 Pull device enabled
0 Pull device disabled
0
PERT
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If this pin is used as XIRQ only a pullup device can be enabled.
1 Pull device enabled
0 Pull device disabled