NXP Semiconductors MC9S12G - Page 208

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
210 NXP Semiconductors
2.4.3.19 Port T Polarity Select Register (PPST)
2.4.3.20 Port S Data Register (PTS)
Address 0x0245 (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W
Reset00000000
Address 0x0245 (G3) Access: User read/write
1
76543210
R0 0
PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W
Reset00000000
Figure 2-20. Port T Polarity Select Register (PPST)
Table 2-39. PPST Register Field Descriptions
Field Description
7-0
PPST
Port T pull device select—Configure pull device polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
1 Pulldown device selected
0 Pullup device selected
Address 0x0248 Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
00000000
Figure 2-21. Port S Data Register (PTS)