NXP Semiconductors MC9S12G - Page 211

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 213
2.4.3.25 Port S Wired-Or Mode Register (WOMS)
2.4.3.26 Pin Routing Register 0 (PRR0)
NOTE
Routing takes only effect if PKGCR is set to select the 20 TSSOP package.
Table 2-44. PPSS Register Field Descriptions
Field Description
7-0
PPSS
Port S pull device select—Configure pull device polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
1 Pulldown device selected
0 Pullup device selected
Address 0x024E Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
WOMS7WOMS6WOMS5WOMS4WOMS3WOMS2WOMS1WOMS0
W
Reset00000000
Figure 2-26. Port S Wired-Or Mode Register (WOMS)
Table 2-45. WOMS Register Field Descriptions
Field Description
7-0
WOMS
Port S wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven
active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit
has no influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
Address 0x024F Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0
W
Reset00000000
Figure 2-27. Pin Routing Register (PRR0)