NXP Semiconductors MC9S12G - Page 210

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
212 NXP Semiconductors
2.4.3.23 Port S Pull Device Enable Register (PERS)
2.4.3.24 Port S Polarity Select Register (PPSS)
Table 2-42. DDRS Register Field Descriptions
Field Description
7-0
DDRS
Port S data direction—
This bit determines whether the associated pin is a general-purpose input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x024C Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
Reset11111111
Figure 2-24. Port S Pull Device Enable Register (PERS)
Table 2-43. PERS Register Field Descriptions
Field Description
7-0
PERS
Port S pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup
device.
1 Pull device enabled
0 Pull device disabled
Address 0x024D Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
Reset00000000
Figure 2-25. Port S Polarity Select Register (PPSS)