NXP Semiconductors MC9S12G - Page 213

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 215
2.4.3.27 Port M Data Register (PTM)
Table 2-50. IOC2 Routing Options
PRR0T21 PRR0T20 IOC2 Associated Pin
0 0 PS5 - IOC2
0 1 PE0 - IOC2
1 0 PAD4 - IOC2
11Reserved
Table 2-51. SCI0 Routing Options
PRR0S1 PRR0S0 SCI0 Associated Pin
0 0 PE0 - RXD, PE1 - TXD
0 1 PS4 - RXD, PS7 - TXD
1 0 PAD4 - RXD, PAD5 - TXD
11Reserved
Address 0x0250 (G1, G2) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R0000
PTM3 PTM2 PTM1 PTM0
W
Reset00000000
Address 0x0250 (G3) Access: User read/write
1
76543210
R000000
PTM1 PTM0
W
Reset00000000
Figure 2-28. Port M Data Register (PTM)
Table 2-52. PTM Register Field Descriptions
Field Description
3-0
PTM
Port M general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose
output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.