NXP Semiconductors MC9S12G - Page 214

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
216 NXP Semiconductors
2.4.3.28 Port M Input Register (PTIM)
2.4.3.29 Port M Data Direction Register (DDRM)
Address 0x0251 (G1, G2) Access: User read only
1
1
Read: Anytime
Write:Never
76543210
R 0 0 0 0 PTIM3 PTIM2 PTIM1 PTIM0
W
Reset00000000
Address 0x0251 (G3) Access: User read only
1
76543210
R000000PTIM1PTIM0
W
Reset00000000
Figure 2-29. Port M Input Register (PTIM)
Table 2-53. PTIM Register Field Descriptions
Field Description
3-0
PTIM
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0252 (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R0000
DDRM3 DDRM2 DDRM1 DDRM0
W
Reset00000000
Address 0x0252 (G3) Access: User read/write
1
76543210
R000000
DDRM1 DDRM0
W
Reset00000000
Figure 2-30. Port M Data Direction Register (DDRM)