NXP Semiconductors MC9S12G - Page 218

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
220 NXP Semiconductors
2.4.3.34 Port P Data Register (PTP)
Table 2-59. API_EXTCLK Routing Options
APICLKS7 API_EXTCLK Associated Pin
0 PB1 (100 LQFP)
PP0 (64/48/32 LQFP)
N.C. (20TSSOP)
1 PS7
Table 2-60. Package Options
PKGCR2 PKGCR1 PKGCR0 Selected Package
111Reserved
1
1
Reading this value indicates an illegal code write or uninitialized factory programming.
1 1 0 100 LQFP
101Reserved
1 0 0 64 LQFP
0 1 1 48 LQFP
010Reserved
0 0 1 32 LQFP
00020 TSSOP
Address 0x0258 (G1, G2) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
Reset00000000
Address 0x0258 (G3) Access: User read/write
1
76543210
R0 0
PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
Reset00000000
Figure 2-35. Port P Data Register (PTP)