Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 225
1
Read: Anytime
Write: Anytime, write 1 to clear
Table 2-67. PIFP Register Field Descriptions
Field Description
7-0
PIFP
Port P interrupt flag—
This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and
Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
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