NXP Semiconductors MC9S12G - Page 376

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
378 NXP Semiconductors
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
0x02F1
76543210
R00000LVDS
LVIE LVIF
W
Reset00000U0U
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
= Unimplemented or Reserved
Figure 10-16. Low Voltage Control Register (CPMULVCTL)
Table 10-15. CPMULVCTL Field Descriptions
Field Description
2
LVDS
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage VDDA is above level V
LVID
or RPM.
1 Input voltage VDDA is below level V
LVIA
and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
0x02F2
76543210
R
APICLK
00
APIES APIEA APIFE APIE APIF
W
Reset00000000
= Unimplemented or Reserved
Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)