NXP Semiconductors MC9S12G - Page 375

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 377
Read: Anytime
Write: Only in Special Mode
10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
10.3.2.13 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
0x003E
76543210
R00000000
W
Reset00000000
= Unimplemented or Reserved
Figure 10-14. Reserved Register (CPMUTEST1)
0x003F
76543210
R00000000
W ARMCOP-Bit
7
ARMCOP-Bit
6
ARMCOP-Bit
5
ARMCOP-Bit
4
ARMCOP-Bit
3
ARMCOP-Bit
2
ARMCOP-Bit
1
ARMCOP-Bit
0
Reset00000000
Figure 10-15. S12CPMU CPMUARMCOP Register