NXP Semiconductors MC9S12G User Manual

Analog-to-Digital Converter (ADC12B16CV2)
MC9S12G Family Reference Manual Rev.1.27
546 NXP Semiconductors
16.3.2.5 ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Table 16-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 FRZ0 Behavior in Freeze Mode
0 0 Continue conversion
01Reserved
1 0 Finish current conversion, then freeze
1 1 Freeze Immediately
Module Base + 0x0004
76543210
R
SMP2 SMP1 SMP0 PRS[4:0]
W
Reset00000101
Figure 16-7. ATD Control Register 4 (ATDCTL4)
Table 16-12. ATDCTL4 Field Descriptions
Field Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 16-13 lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
Refer to Device Specification for allowed frequency range of f
ATDCLK
.
Table 16-13. Sample Time Select
SMP2 SMP1 SMP0
Sample Time
in Number of
ATD Clock Cycles
000 4
001 6
010 8
011 10
100 12
101 16
110 20
f
ATDCLK
f
BUS
2PRS1+
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NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English