Analog-to-Digital Converter (ADC12B16CV2)
MC9S12G Family Reference Manual Rev.1.27
548 NXP Semiconductors
4
MULT
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
3–0
CD, CC,
CB, CA
Analog Input Channel Select Code — These bits select the analog input channel(s). Table 16-15 lists the
coding used to select the various analog input channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN16 to AN0.
Table 16-15. Analog Input Channel Select Coding
SC CD CC CB CA
Analog Input
Channel
00000 AN0
0001 AN1
0010 AN2
0011 AN3
0100 AN4
0101 AN5
0110 AN6
0111 AN7
1000 AN8
1001 AN9
1010 AN10
1011 AN11
1100 AN12
1101 AN13
1110 AN14
1111 AN15
Table 16-14. ATDCTL5 Field Descriptions (continued)
Field Description
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