Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12G Family Reference Manual Rev.1.27
642 NXP Semiconductors
Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale
value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the
8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater
range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value
in the PWMSCLA register.
NOTE
Clock SA = Clock A / (2 * PWMSCLA)
When PWMSCLA = $00, PWMSCLA value is considered a full scale value
of 256. Clock A is thus divided by 512.
Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock
SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.
NOTE
Clock SB = Clock B / (2 * PWMSCLB)
When PWMSCLB = $00, PWMSCLB value is considered a full scale value
of 256. Clock B is thus divided by 512.
As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for
this case will be E (bus clock) divided by 4. A pulse will occur at a rate of once every 255x4 E cycles.
Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate.
Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock
at an E divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.
Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper
rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or
PWMSCLB is written prevents this.
NOTE
Writing to the scale registers while channels are operating can cause
irregularities in the PWM outputs.
19.4.1.3 Clock Select
Each PWM channel has the capability of selecting one of four clocks, clock A, clock SA, clock B or clock
SB. The clock selection is done with the PCLKx control bits in the PWMCLK register and PCLKABx
control bits in PWMCLKAB register. For backward compatibility consideration, the reset value of
PWMCLK and PWMCLKAB configures following default clock selection.
For channels 0, 1, 4, and 5 the clock choices are clock A.
For channels 2, 3, 6, and 7 the clock choices are clock B.
NOTE
Changing clock control bits while channels are operating can cause
irregularities in the PWM outputs.
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