Timer Module (TIM16B6CV3)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 723
22.3.2.1 Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
22.3.2.2 Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
1
The register is available only if corresponding channel exists.
Module Base + 0x0000
76543210
R
RESERVED RESERVED IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
W
Reset00000000
Figure 22-4. Timer Input Capture/Output Compare Select (TIOS)
Table 22-2. TIOS Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
5:0
IOS[5:0]
Input Capture or Output Compare Channel Configuration
0 The corresponding implemented channel acts as an input capture.
1 The corresponding implemented channel acts as an output compare.
Module Base + 0x0001
76543210
R00000000
W RESERVED RESERVED FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Reset00000000
Figure 22-5. Timer Compare Force Register (CFORC)
Table 22-3. CFORC Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
5:0
FOC[5:0]
Note: Force Output Compare Action for Channel 5:0 — A write to this register with the corresponding data
bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
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