NXP Semiconductors MC9S12G User Manual

96 KByte Flash Module (S12FTMRG96K1V1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 983
All assigned bits in the FERCNFG register are readable and writable.
28.3.2.7 Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Offset Module Base + 0x0005
76543210
R000000
DFDIE SFDIE
W
Reset00000000
= Unimplemented or Reserved
Figure 28-10. Flash Error Configuration Register (FERCNFG)
Table 28-14. FERCNFG Field Descriptions
Field Description
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 28.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 28.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 28.3.2.8)
Offset Module Base + 0x0006
76543210
R
CCIF
0
ACCERR FPVIOL
MGBUSY RSVD MGSTAT[1:0]
W
Reset1000000
1
1
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 28.6).
0
1
= Unimplemented or Reserved
Figure 28-11. Flash Status Register (FSTAT)

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English