96 KByte Flash Module (S12FTMRG96K1V1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 989
28.3.2.9.1 P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 28-21 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
28.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
Table 28-21. P-Flash Protection Scenario Transitions
From
Protection
Scenario
To Protection Scenario
1
1
Allowed transitions marked with X, see Figure 28-14 for a definition of the scenarios.
01234567
0
XXXX
1
XX
2
XX
3
X
4
XX
5
XXXX
6
XXXX
7
XXXXXXXX
Offset Module Base + 0x0009
76543210
R
DPOPEN DPS[6:0]
W
Reset F
1
1
Loaded from IFR Flash configuration field, during reset sequence.
F
1
F
1
F
1
F
1
F
1
F
1
F
1
Figure 28-15. EEPROM Protection Register (EEPROT)
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